As the size of planar transistors has been steadily decreased, they are expected to suffer from undesirable short channel effects, especially in 32 nm and smaller technologies. An OTP (one-time programmable) memory in MOS (Metal Oxide Silicon) generally takes advantages of thin-oxide breakdown, but experiences disadvantages, including unreliability for production. Because the heat generated in a P/N junction can easily be dissipated in a planar structure, spikes in the P/N junction that can be shorted due to dopant migration or inter-diffusion of the contact alloy require an extreme high current, such as an ESD zap, to reliably break the junction. Spikes usually result from a P/N junction being reverse-biased for a long time. An approach tying the gate to the drain and applying a high voltage to the source for using MOS as OTP is also unreliable.